基于BU-61580总线控制器的接口及容错设计  

Design of Interface and Fault-tolerant Scheme of Bus Controller based on BU-61580

作　　者：马睿[1,2] 张会新[1,2] 杨慧[3] 张凤英[1,2] 翟成瑞[1,2] 赵杰[1,2] 

机构地区：[1]中北大学电子测试技术重点实验室,太原030051 [2]中北大学仪器科学与动态测试教育部重点实验室,太原030051 [3]中国运载火箭技术研究院,北京100000

出　　处：《计算机测量与控制》2014年第12期4163-4165,共3页Computer Measurement &Control

基　　金：国家自然科学基金项目(61335008)

摘　　要：针对RS-422接口与1553B总线接口无法直接进行高可靠性数据通信,提出了一种基于BU-61580总线控制器的接口及容错设计;设计采用1553B接口芯片BU-61580,通过FPGA控制完成了RS-422与1553B的接口控制及二者之间的数据处理;在硬件接口设计的基础上,设计IP-CORE完成BU-61580的芯片配置,并通过增加容错设计提高了总线控制器数据通信的可靠性;经测试结果显示,计算机通过总线控制器与RT终端通信稳定、可靠,并应用于某测试系统中。For the case RS-422 interface can not directly communicate with 1553B bus interface with high reliability,a interface and fault-tolerant design based on BU-61580 bus controller is proposed.The design uses 1553B interface chip BU-61580 that completes interface control and data processing between RS-422 and 1553B by FPGA control.On the basis of the design of the hardware interface,it completes BU-61580 chip configuration by designing IP-CORE,and improves the reliability of data communication of bus controller increasing the fault-tolerant design.The test results show that communication with bus controller and RT terminal is stable,and it is applied in a test system.

关 键 词：1553B总线 RS-422 BU-61580 容错设计 FPGA 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]