基于FPGA的改进误差扩散加网算法实现  

REALISING FPGA-BASED IMPROVED ERROR DIFFUSION SCREENING ALGORITHM

作　　者：赵莲清[1] 李树[1] 

机构地区：[1]华北电力大学电气与电子工程学院,北京102206

出　　处：《计算机应用与软件》2014年第11期161-164,共4页Computer Applications and Software

摘　　要：传统的误差扩散算法内存占用率高,加网速度慢。通过结合传统算法和并行优化算法,提出一种基于FPGA的算法改进方案并加以实现,大大减少了资源占用率并提高了加网速度。以FS误差扩散算法为例对加网结果进行分析表明,优化后的算法效果良好,基于可编程器件的数字加网不再依赖大容量存储,并使得实时加网成为可能。Traditional error diffusion algorithm has the problems of high memory occupancy and low screening speed.In this paper,by combining traditional algorithms and parallel optimisation algorithm,we propose an FPGA-based algorithm optimisation scheme and implement it,the resource occupancy rate is reduced greatly and the screening speed is improved as well.Furthermore,FS error diffusion algorithm is used as the example to analyse screening result.Analysis outcome shows that the optimised algorithm has good effect.Digital screening based on PLC no longer relies on mass storage,and the real-time screening will become possible.

关 键 词：数字加网 FPGA 误差扩散 并行计算 

分 类 号：TP391.8[自动化与计算机技术—计算机应用技术]