基于AES的可重构加密系统的FPGA设计  

FPGA design of reconfigurable encryption system based on AES

作　　者：杨斐[1] 彭鹏[2] 

机构地区：[1]湖北理工学院计算机学院,湖北黄石435003 [2]东南大学软件学院,江苏南京210096

出　　处：《微型机与应用》2014年第24期2-4,共3页Microcomputer & Its Applications

基　　金：湖北省教育厅科学技术研究项目(B2013064)

摘　　要：针对传统软件加密方法在速度和资源消耗上的不足,提出了基于AES高级加密标准的硬件设计方案。采用了目前流行的EDA技术,在FPGA芯片上实现一种可重构的加密系统,利用硬件描述语言实现加密算法中的移位、S盒置换函数、线性反馈移位寄存器等功能,设计输入、模型综合、布局布线、功能仿真都在Altera公司的Quartus II开发平台中完成,产生的下载文件通过Cyclone系列的FPGA芯片进行测试。实验结果表明,该系统具有独特的物理安全性和高速性。In accordance with the deficiency of traditional software encryption methods in terms of speed and resource consumption, the paper proposes a hardware design program based on AES （Advanced Encryption Standard）. The program adopts the currently-popular EDA technology, achieves a reconfigurable encryption system on FPGA chip, and uses hardware description language, to achieve a series of functions in encryption algorithm, such as shift, S cartridge replacement functions, and linear feedback shifting register. Design input, model synthesis, placement and routing, functional simulation were all accomplished on Ahera＇s Quartus II development platform. Besides, the downloaded files were tested by the FPGA chip of Cyclone series. The experimental result shows that the system has unique physical security and high speed.

关 键 词：信息安全 高级加密标准 现场可编程门阵列 Quartus Ⅱ 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]