一种提高安全计算机可靠性的内存检测设计  

Design of memory detection for raising reliability of vital computer

作　　者：徐军 王澜 耿进龙 崔丹 房增华 

机构地区：[1]卡斯柯信号有限公司研发中心,上海200071

出　　处：《铁路计算机应用》2014年第10期47-52,共6页Railway Computer Application

摘　　要：目前应用在嵌入式系统的各种内存检测方案,很难均衡地满足内存检测性能要求:比较高的检测覆盖率、比较低的硬件开销、比较高的检测速度。根据轨旁安全计算机的系统特性和安全性要求,提出了一种软硬件相结合的内存内建测试架构方案,利用硬件BIST方案来检测高层次内存故障和软件BIST方案来覆盖低层次内存故障。实际项目应用结果显示,该混合内存检测方案可以有效地减少硬件开销和降低检测时间,并提高内存故障检测覆盖率至99%,使系统能够满足高实时性、高安全性的要求。Design scheme of memory detection applied to embedded devices currently,seemed difficult to meet three performances：high diagnostic coverage,low hardware cost and high testing speed.According to system property and safety requirement of track-side vital computer,the paper presented a design scheme of memory detection for safety device,combined hardware with software,used BIST hardware to detect high level memory fault,used BIST software to test low level fault.Experimental results showed that the hybrid memory detection methods could effectively detect memory failure and fault with high reliability requirement and high safety requirement,obtain a general increase in the diagnostic coverage to 99％,reduce hardware cost and testing time,meet the needs of highly real-time and high security.

关 键 词：内存故障 安全 内存检测 

分 类 号：U29[交通运输工程—交通运输规划与管理] TP39[交通运输工程—道路与铁道工程]