A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers  

作　　者：Ting GUO Zhi-qun LI Qin LI Zhi-gong WANG 

机构地区：[1]School of Integrated Circuits, Southeast University [2]Institute of RF- & OE-ICs, Southeast University

出　　处：《Journal of Zhejiang University-Science C(Computers and Electronics)》2014年第12期1200-1210,共11页浙江大学学报C辑（计算机与电子（英文版）

基　　金：Project supported by the National Basic Research Program of China(No.2010CB327404);the National Natural Science Foundation of China(No.60901012)

摘　　要：A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.A 37 GHz wide-band programmable divide-by-N frequency divider （FD） composed of a divide-by-2 divider （acting as the first stage） and a divider with a division ratio range of 273 330 （acting as the second stage） has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider （with high speed） and the divide-by-8/9 prescaler employ dynamic current-mode logic （DCML） structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as 20 dBm at 32 GHz and the phase noise at 37 GHz is less than -130 dBc/Hz at an offset of 1MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730μm ×475 μm.

关 键 词：WIDE-BAND Divide-by-N Frequency divider Dynamic current-mode logic(DCML) Pulse and swallow counters CMOS 

分 类 号：TN772[电子电信—电路与系统]