基于多层网络的片上网络可靠测试结构  

Reliable Test Structure for Network on Chip Based on Multilayer Network

作　　者：俞剑明[1] 周炜[1] 虞志益[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2015年第1期275-278,283,共5页Computer Engineering

基　　金：国家自然科学基金资助项目(61103008);上海市科委集成电路专项基金资助项目(12511503700);国家科技重大专项基金资助项目(2011ZX03003-003-03)

摘　　要：为解决片上网络测试问题,提出高可靠高并行度的片上网络测试结构。使用多层网络,在普通的片上网络上增加全局的广播网络和汇集测试结果的汇集网络。利用其冗余特性,有效保证测试部件的可靠性,同时提高并行度,节约测试时间。提出完备的路由器内测试方法,结合多层网络实现全面的片上网络测试。实验结果表明,该多层网结构在100核时的面积开销比内建自修复(BISR)结构减小56%,并且其测试时间比BISR结构减少85.8%,测试覆盖率达到100%。This paper proposes a new test architecture with high reliability and high parallelism. It adds a broadcasting network and a gathering network controlled by the broadcasting layer on top of the network under test. With the redundancy of these two networks,the robustness of the test access interface can be improved. Meanwhile,more test parallelism is brought and huge decrease is achieved in test time. Complete inner router test methods are also developed.Combined with the multilayer test access method,a complete and reliable test platform is got for Network on Chip（No C）. The result shows the multilayer network takes 56% less area and uses 85. 8% less test time than Build-in Self-repair BISR in 100-core system. And the fault coverage of the design achieves 100%.

关 键 词：多核处理器 片上网络 多层网络 链路错误 控制错误 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]