基于EG LDPC码的快速译码器的FPGA设计与实现  

FPGA implementation of a fast decoder for EG LDPC codes

作　　者：马克祥 张海林[2] 

机构地区：[1]中国电子科技集团公司电子科学研究院,北京100041 [2]西安电子科技大学通信工程学院,陕西西安710071

出　　处：《西北大学学报（自然科学版）》2014年第6期893-897,共5页Journal of Northwest University（Natural Science Edition）

基　　金：国家自然科学基金资助项目(61072069);教育部科学技术研究重点(重大)基金资助项目(2010ZX03002-005)

摘　　要：针对Euclidean Geometry(EG)-LDPC码码字的循环特性以及FWBF(fast weighted bit flipping)算法的算法结构设计高速LDPC译码器。具体实现方法如下:首先通过对RAM进行合理的划分,赋给不同的RAM相应的规则号和初始地址值保证数据的无冲突存取,然后通过向量化操作实现运算数据的高速存取。此外,校验式品质计算模块通过引入一种新型的树形搜索电路来降低该模块的功耗和延迟。最后,对EG255码采用5路并行模式,在Cyclone III EP3C120F780C7芯片上实现,信息吞吐量可达75.98Mbs,占用芯片逻辑资源不超过23%,RAM资源不超过4%。A FWBF decoder is designed to implement the high-speed decoding of EG-LDPC codes according to their cyclic characteristic. Specially, RAMs are divided and provided proper regular numbers and initial addresses to implement conflict-free access of the operation data, while vectorization is introduced to implement the high-speed access. Furthermore, a new tree-sorting structure is proposed to lower the power consumption and delay of computing metric values. The decoder for EG（255,173 ） code with five parallel computation units is implemented on Cyclone III EP3C120F780CT, and can work with processing rate up to 75.89Mbps. Because this decoder only consumes 23% logic resource and 4% RAM resource, its throughput can be simply improved with more parallel computation units.

关 键 词：LDPC 加权比特翻转算法 向量化 无冲突存取. 

分 类 号：TN911.22[电子电信—通信与信息系统]