用于三维堆叠芯片的通用网络服务片设计  

Design of Generic Network Service Die Used in 3D Stacked IC

作　　者：吴际[1] 谢冬青[1] 唐琳[1] 

机构地区：[1]广州大学计算机科学与教育软件学院,广州510006

出　　处：《系统仿真学报》2014年第11期2727-2733,共7页Journal of System Simulation

基　　金：国家自然科学基金广东省联合基金(U1135002);广东省高等学校科技创新重点项目(cxzd1144);广州市教改项目(2013A022)

摘　　要：在三维集成技术中,让制造检测好的已知合格片在不同的三维芯片设计中复用可有效降低成本。设计了一种采用通用网络服务片(GNSD)来构建三维片上网络的通用网络(GNet),并以一个64核处理器为实验对象,分别采用传统的三维片上网络设计中成本驱动的设计和性能驱动的设计,和采用GNet的设计来实现该处理器。对3种设计进行仿真,对比其吞吐率、时延、功耗及成本,证明GNet不仅仅在成本上有突出的优势,在性能上也优于传统的三维设计。In 3D integration technology, the reuse of KGDs （known good dies） in different 3D stacks can cut down cost effectively. GNet, a 3D architecture for reusing generic network service dies, was proposed to construct a network-on-chip （NoC） by virtue of exploiting reuse of generic network service dies, （GNSDs）. Whereafter a 64-core processor was studied, and implementations using traditional 3D NoC design, including cost-driven design and performance-driven design, and GNet architecture were compared. The three kinds of implementations were emulated, and throughput, latency, energy and fabrication costs of them were analyzed. It turns out that GNet architecture is superior to traditional 3D NoC not only in cost but also in performance.

关 键 词：三维芯片 三维片上网络 网络性能分析 众核处理器设计 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]