Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET using trench-based structure  

作　　者：赵迪 罗谦 王向展 于奇 崔伟 谭开洲 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China [2]Science and Technology on Analog Integrated Circuit Laboratory

出　　处：《Journal of Semiconductors》2015年第1期101-104,共4页半导体学报（英文版）

基　　金：Project supported by the Innovative Fund of State Key Laboratory of Electronic Thin Films and Integrated Devices(No.CXJJ201103);the Fund of Analog Integrated Circuit Key Laboratory(No.9140C090301120C09035);the Scientific Research Project of Land and Resources Department of Sichuan Province(No.KJ-2013-12 2200199)

摘　　要：A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer（CESL）, whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a 2：5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from 333 into 256 MPa, which leads to a significant improvement of the device＇s I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer（CESL）, whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a 2：5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from 333 into 256 MPa, which leads to a significant improvement of the device＇s I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.

关 键 词：CESL trench strained NMOSFET SiN 

分 类 号：TN386[电子电信—物理电子学]