一种0.18μm CMOS可编程分频器的设计  

Design of a 0.18 μm CMOS Programmable Frequency Divider

作　　者：郑立博[1] 张长春[1] 郭宇锋[1] 方玉明[1] 刘蕾蕾[1,2] 

机构地区：[1]南京邮电大学电子科学与工程学院,南京210003 [2]东南大学毫米波国家重点实验室,南京210096

出　　处：《微电子学》2014年第6期813-817,共5页Microelectronics

基　　金：国家自然科学基金资助项目（61076073）;中国博士后科学基金资助项目（2012M521126）;江苏省自然科学基金资助项目（BK2012435）;东南大学毫米波国家重点实验室开放基金资助项目（K201223）;南京邮电大学科研启动金资助项目（NY211016）

摘　　要：采用标准0.18μm CMOS工艺,设计了一种可编程分频器。基于基本分频单元的特殊结构,对除2/除3单元级联式可编程分频器的关键模块进行改进,将普通的CML型锁存器集成为包含与门的锁存器,提高了电路的集成度,有效地降低了电路功耗,提升了整体电路速度,并使版图更为紧凑。后仿真结果表明,在1.8V电源电压,输入频率fin=1GHz的情况下,可实现任意数且步长为1的分频比,相位噪声为-173.1dBc/Hz@1 MHz,电路功耗仅为9mW。A programmable frequency divider was proposed in a 0.18 μm standard CMOS. Based on the special structure of basic dividing cell, the 2/3 dividing cell was improved, which was the key module of the cascaded programmable frequency divider. The ordinary CML D-latch was integrated into AND_latch, thus increasing the chip integration, effectively reducing the power consumption of the circuit, raising the overall circuit speed, and tightening the layout more compact. The post simulation results showed that from a supply voltage of 1.8 V and an input frequency of 1 G-Hz, arbitrary integer frequency ratio was available. The circuit had a phase noise of --173.1 dBc/Hz @ 1 MHz and a power consumption of 9 mW.

关 键 词：可编程分频器 除2/除3分频单元 电流模逻辑 相位噪声 

分 类 号：TN453[电子电信—微电子学与固体电子学]