基于粗粒度可重构阵列结构的多标准离散余弦变换设计  

Design of Multi-standard Discrete Cosine Transform Based on Coarse-grained Reconfigurable Array

作　　者：陈锐[1,2] 杨海钢[1] 王飞[1] 贾瑞[1,2] 喻伟[1,2] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100190

出　　处：《电子与信息学报》2015年第1期206-213,共8页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61204045;61271149);中国科学院;国家外国专家局创新团队国际合作伙伴计划资助课题

摘　　要：在视频信号的编解码流程中,离散余弦变换(DCT)是一个至关重要的环节,其决定了视频压缩的质量和效率。针对8×8尺寸的2维离散余弦变换,该文提出一种基于粗粒度可重构阵列结构(Coarse-Grained Reconfigurable Array,CGRA)的硬件电路结构。利用粗粒度可重构阵列的可重配置的特性,实现在单一平台支持多个视频压缩编码标准的8×8 2维离散余弦变换。实验结果显示,这种结构每个时钟周期可以并行处理8个像素,吞吐率最高可达1.157×109像素/s。与已有结构相比,设计效率和功耗效率最高可分别提升4.33倍和12.3倍,并能够以最高30帧/s的帧率解码尺寸为4096×2048,格式为4:2:0的视频序列。Discrete Cosine Transform（DCT） plays an important role in the codec process of video signals, and has a significant influence on the compression efficiency and quality. In this paper, a Coarse-Grained Reconfigurable Array（CGRA） based hardware architecture is proposed for 8-point 2D DCT. Through the reconfiguration of coarse-grained reconfigurable array, the proposed architecture is capable of supporting 8×8 2D discrete cosine transform of the multiple video compression coding standards in a single platform. The experimental results show that the proposed architecture is able to parallel process 8 pixels in a cycle, and the throughput achieves up to 1.157×109 pixels per second. The design efficiency and power efficiency is about 4.33 times and 12.3 times higher than existing works respectively. Moreover, the proposed architecture can support real-time decoding of 4096×2048 at 30 fps（4：2：0） video sequences.

关 键 词：粗粒度可重构阵列 视频压缩 离散余弦变换 功耗效率 

分 类 号：TN402[电子电信—微电子学与固体电子学]