256MHz采样71dB动态范围连续时间ΣΔADC设计  

Continuous time ΣΔADC design with 256MHz sampling and 71dB DR

作　　者：杨银堂[1] 袁俊[1] 张钊锋[2] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西西安710071 [2]中国科学院上海高等研究院信息科学与技术研究部,上海201203

出　　处：《西安电子科技大学学报》2015年第1期10-15,共6页Journal of Xidian University

基　　金：国家重大专项资助项目(2010ZX03006-003-02)

摘　　要：宽带连续时间ΣΔ型数模转换器大量用于无线通信领域.设计了采用三阶4bit连续时间调制器架构.为降低时钟抖动的影响,采用不归零数模转换器反馈脉冲,通过引入半个时钟周期延时来改善环路异步问题,以补偿环路延时对性能的影响.还从电路、算法和版图方面来降低反馈数模转换器失配的影响.由于米勒补偿增加了电容而增大功耗,因此这里采用前馈补偿技术,设计了一款低功耗、高速的运算放大器.最后基于0.13μm工艺,在256MHz采样频率、1.2V电源电压下,在8MHz带宽内信噪失真比达到62.5dB和71dB动态范围,功耗为15mW.A wide bandwidth continuous time ΣΔADC is widely used in the wireless communication field. A ΣΔADC with the 3 order 4 bit modulator is designed with the 256 MHz sampling frequency. In order to reduce the clock jitter, the nonreturn-to-zero （NRZ） DAC feedback pulse is used. And the loop asynchronous problem is improved by introducing a half of clock cycle delay. Also how to reduce the effect of the DAC mismatch is discussed. A low voltage, low power, and high speed operational amplifier is designed with feedforward compensation technology. Finally, based on the 0.13 μm technology, the SNDR is 62.5 dB and DR is 71dB with a 1.2V supply.

关 键 词：模数转换器 连续时间 ΣΔ型数模转换器 

分 类 号：TN4[电子电信—微电子学与固体电子学]