基于现场可编程门阵列的加速器同步控制器设计  

Design of synchronous controller for accelerator based on FPGA

作　　者：徐卫彬[1,2] 郭玉辉[1] 郑亚伟[1,2] 罗冰峰 贾欢[1,2] 

机构地区：[1]中国科学院近代物理研究所,兰州730000 [2]中国科学院大学,北京100049

出　　处：《强激光与粒子束》2015年第1期197-200,共4页High Power Laser and Particle Beams

基　　金：中国科学院战略性先导科技专项资助课题项目(XDA03021503)

摘　　要：针对加速器驱动次临界系统(ADS)注入器Ⅱ的控制中对于同步触发信号的要求,设计了基于现场可编程门阵列(FPGA)的高精度同步控制器,它能为加速器设备提供同步工作所需的脉冲信号。控制器采用粗延时结合精延时的方式,FPGA实现粗延时,专用延时芯片实现精延时,提高了延时精度,同时增大了延时、脉宽及周期的调节范围。测试结果表明,该控制器输出脉冲的最小延时步距为0.25ns,延时、脉宽及周期调节范围为1μs^2s,周期抖动的标准偏差为70ps。该控制器输出信号满足要求,程序界面操作简便,通过串口RS-422远程控制稳定可靠。A synchronous controller based on FPGA is designed to meet the requirements in the process of controlling injectorⅡ of accelerator driven sub-critical system（ADS）.It provides 4synchronous pulse signals for some equipments in injectorⅡ.The controller combines coarse delay based on FPGA and fine delay based on dedicated delay chip to improve the precision of delay and increase the adjustable ranges of period,pulse width and delay.The delay per step is 0.25 ns.Delay,period and pulse width range from 1μs to 2s.The standard deviation of period jitter is 70 ps.The output signals meet the specified requirements.The program of this controller is easy to operate,and the remote control is stable and reliable.

关 键 词：加速器驱动次临界系统 现场可编程门阵列 同步 脉冲 延时 

分 类 号：TP29[自动化与计算机技术—检测技术与自动化装置]