HEVC帧内预测Planar和DC模式算法的并行化设计  

Efficient Parallel Design of Planar and DC Mode in HEVC Intra Prediction

作　　者：谢晓燕[1] 徐卫芳[1] 刘帆[1] 

机构地区：[1]西安邮电大学计算机学院,陕西西安710061

出　　处：《电视技术》2015年第5期4-8,60,共6页Video Engineering

基　　金：国家自然科学基金项目(61272120);陕西省自然科学基础研究计划项目(2013JC2-32)

摘　　要：针对HEVC帧内预测Planar和DC模式算法的特点,提出实现这两种模式的并行化方法。该方法是通过分析推导Planar和DC模式算法之间的可并行性,以西安邮电大学自主设计的一款面向图形、图像应用的阵列处理器PAAG(Polymorphic Array Architecture for Graphics and Image Processing)平台为基础,采用最优的数据分配方式,合理地设计了多处理单元并行工作的算法程序。实验结果表明Planar预测模式和DC预测模式在多处理单元上的并行实现,相比于单核的串行运算速度分别提高了84%和81%,串/并行加速比分别达到6.34和5.44。该并行化算法减少了视频的编解码时间,其数据分配方案对于帧内预测算法在多核结构上的并行化研究也有一定的参考价值。According to the algorithm characteristics of Planar and DC mode in HEVC intra prediction, a parallel processing method of the two prediction modes was proposed. The paper well designed a parallel algorithm program based on PAAG（PAAG, A Polymorphic Array Architecture for Graphics and Image Processing, an image array processor designed by Xi’an University of Posts and Telecommunications） processor platform, by analyzing and deriving the parallelism of Planar prediction mode and DC prediction mode, adopting the best data distribution, and making full use of multiple processing elements of PAAG. The experimental results show that compared with serial computing, the parallel achievement of Planar prediction mode and the DC prediction mode on the processing elements, reduced computing time of 84% and 81%, gaining speedups of 6.34 and 5.44 times, respectively. The parallel algorithm significantly reduces time video codec and the data distribution scheme has also a certain reference value for the parallelization research of intra prediction algorithm based on multi-core structure.

关 键 词：HEVC 帧内预测 并行化 数据分配 阵列处理器 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]