A write buffer design based on stable and area-saving embedded SRAM for flash applications  

作　　者：CAO Hua Min HUO Zong Liang WANG Yu LI Ting LIU Jing JIN Lei JIANG Dan-Dan ZHANG Deng Jun LI Di LIU Ming 

机构地区：[1]Institute of Microelectronics, Chinese Academy of Sciences [2]College of Communication Engineering, Chengdu University of Information Technology [3]Guangdong Berg Micro Co., Ltd.

出　　处：《Science China(Technological Sciences)》2015年第2期357-361,共5页中国科学（技术科学英文版）

基　　金：supported by the MOST(Grant Nos.2010CB934200 and 2011CBA00600);the National Natural Science Foundation of China(Grant Nos.61176073 and 61221004)

摘　　要：This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.

关 键 词：write buffer embedded SRAM FLASH 65 nm technology 2 kb 128 Mb 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TB485.1[自动化与计算机技术—计算机科学与技术]