A high linearity downconverter for digital broadcasting system  

作　　者：李松亭 李建成 谷晓忱 王宏义 庄钊文 

机构地区：[1]College of Electronic Science and Engineering,National University of Defense Technology

出　　处：《Journal of Semiconductors》2014年第12期114-122,共9页半导体学报（英文版）

基　　金：supported by the Science and Technology Innovation Project for the Postgraduates of National University of Defense Technology

摘　　要：An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 m A under a supply of 1.2 V.An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 m A under a supply of 1.2 V.

关 键 词：current-mode downconverter CMOS switching pair DC offset calibration direct conversion receiver LINEARITY Sallen-Key low-pass filter 

分 类 号：TN934.3[电子电信—信号与信息处理] TN943.2[电子电信—信息与通信工程]