基于CMOS图像传感器列级ADC的数字双采样  

Digital Double Sampling on Column Parallel ADC for CMOS Image Sensor

作　　者：徐江涛[1] 贾文龙[1] 高静[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《南开大学学报（自然科学版）》2015年第1期61-66,共6页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：国家自然科学基金(61036004)

摘　　要：提出了一种用于CMOS图像传感器的数字双采样10位列级模数转换器.比较器采用失调消除技术,数字双采样通过加/减计数器实现,使复位信号和像素信号的量化结果在数字域做差,消除了像素输出产生的固定模式噪声;列电路由一个比较器、一个计数器和一个锁存选通器组成.采用GSMC 0.18μm标准CMOS工艺对电路进行设计,一个完整的A/D转换时间为11μs,使用Cadence spectre进行仿真,结果表明:ADC的信噪失真比为57.86dB,有效位数9.32,列电路功耗为58.24μW,由比较器的失调和延迟产生的误差可以减小50%.A 10 bits column parallel analog-to-digital convertor with digital double sampling for CMOS image sensor is described.Offset cancellation is used in the comparator;the up/down ripple counter realizing digital double sampling digitally subtracts the conversion of the reset signal from the sensor signal so that the column fixed-pattern noise could be eliminated.The column circuit consists of a comparator,a ripple counter and a selection latch.The proposed ADC has been designed in 0.18μm standard CMOS process.A whole analog-to-digital conversion time is 11μs.Simulated with Cadence spectre,the signal-to-noise and distortion ratio of the proposed ADC is 57.86 dB,ENOB is 9.32,and the column consumption is 58.24μW.The error caused by offset and delay time of the comparator could be decreased by 50 percent.

关 键 词：CMOS图像传感器 数字双采样 列级模数转换器 

分 类 号：TN47[电子电信—微电子学与固体电子学]