一种分段式数控延迟线的设计  

Design of a Segmented DCDL

作　　者：万贤杰[1] 刘军[1] 付东兵[2] 

机构地区：[1]模拟集成电路重点实验室,重庆400060 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2015年第1期32-35,共4页Microelectronics

摘　　要：简要介绍了当前集成电路延迟调节的主流技术。针对工程应用,提出了一种分段式数控延迟线(DCDL)的设计方法,解决了延迟调节精度和调节范围之间的矛盾,具有面积小、线性度好和调节范围大等优点。基于0.18μm 1P5M CMOS工艺,对电路进行流片。测试结果显示,设计的分段型数控延迟线的调节精度为12ps,动态范围为4ns。The mainstream technology of IC adjustable delay was briefly introduced.According to the engineering application,a method to design segmented digitally controlled delay line was presented,which had made the tradeoff between adjustable delay precision and dynamic range.The designed circuit featured small die area,good linearity and large adjustable range.It was fabricated in 0.18μm lP5 MCMOS process.Test results showed that the precision of the proposed segmented DCDL was 12 ps,and the dynamic range was 4ns.

关 键 词：数控延迟线 门延迟 三态反相器 内插 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN79