面向非写分配高速缓存的一致性协议及实现  

Cache coherence protocol and implementation for multiprocessors with no-write-allocate caches

作　　者：修思文[1] 黄凯[1] 余慜[1] 谢天艺 葛海通 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027 [2]杭州中天微系统有限公司,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2015年第2期351-359,共9页Journal of Zhejiang University：Engineering Science

基　　金：国家科技重大专项基金资助项目(2009ZX01030-001-002);国家自然科学基金资助项目(61100074)

摘　　要：针对现有的高速缓存一致性协议应用在基于写回、非写分配缓存的多核处理器的缺点,提出一种新颖的基于写干涉的一致性协议,并加以硬件实现.采用写干涉协议,在处理器产生写缺失操作时,可以把数据直接写到系统中其他处理器有效的该高速缓存行中;支持"脏数据"的延迟回写和缓存间的数据拷贝;且系统中只要存在有效的被请求的缓存行就可以提供数据,避免不必要的共享存储器访问.实验结果表明,该文提出的写干涉协议与MOESI协议相比,显著减少了对共享存储器的访问,提高了整个系统性能,同时大幅降了低动态功耗.Against the disadvantages of existing cache coherence protocols for write-back and no-write- allocate caches, a novel write intervention based protocol was proposed and hardware implemented. Taking advantage of this protocol, in some cases the data can be directly written to the peer caches when write miss occurs, Furthermore, both delayed write-back mechanism o[ dirty data and cache-to-cache copy are supported. And the requested data can be provided as long as there is at least one valid corresponding cache line, avoiding the unnecessary access of the shared memory. Experimental results show that, in comparison to MOESI protocol, the proposed protocol can significantly reduce the accesses of the shared memory, save the dynamic power consumption and power consumption, and improve the performance of the whole system.

关 键 词：非写分配 多核处理器 高速缓存一致性协议 写干涉 

分 类 号：TN47[电子电信—微电子学与固体电子学]