全插值分像素运动估计VLSI结构  

VLSI architecture for fractional-pixel motion estimation with full interpolation

作　　者：孔睿[1] 余宁梅[1] 路伟[1] 王冬芳[1] 任茹[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,西安710048

出　　处：《计算机工程与应用》2015年第3期162-165,170,共5页Computer Engineering and Applications

基　　金：陕西省自然科学基础研究计划项目(No.2011JQ8032);陕西省重点学科建设专项资金(No.107080903)

摘　　要：提出一种高效的分像素运动估计VLSI结构。通过采用对整个搜索窗口进行并行插值,并设计数据路由结构对数据流进行分配存储的方法,在节省存储空间的同时,有效降低了存储器的访问次数,提高了数据利用率,解决了分像素运动估计数据存储量大、搜索窗口访存次数多以及搜索时间长的问题。在SMIC 0.13μm工艺下,用Synopsys DC进行逻辑综合。在时钟频率300 MHz下,处理1080P的视频图像,速度可以达到65 frame/s。An efficient VLSI architecture for fractional-pixel motion estimation is proposed. Parallel interpolation is applied for the entire search window and a data routing structure is designed for the allocation and storage of the data stream. By this method, the storage space is saved, at the same time, the frequency of memory access is effectively reduced and the data utilization is improved. The problem of large data storage, too much memory access and long searching time in fractional-pixel motion estimation is solved. After logic synthesis by Synopsys DC in the condition of SMIC 0.13 μm process,under 300 MHz clock frequency, the speed can reach 65 frame/s to handle 1080 P video images.

关 键 词：分像素运动估计 超大规模集成电路(VLSI) 实时插值 数据路由 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]