A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time  

作　　者：LIU LiFang WU Dong LIU XueMei HUO ZongLiang LIU Ming PAN LiYang 

机构地区：[1]Institute of Microelectronics, University of Tsinghua [2]Tsinghua National Laboratory for Information Science and Technology [3]Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Science China(Information Sciences)》2015年第4期154-161,共8页中国科学（信息科学）（英文版）

基　　金：supported by National Basic Research Program of China (973 Program) (Grant No. 2011CBA00602);National Nature Science Foundation of China (Grant No. 61106102)

摘　　要：A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm tech- nology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines （WLs） and 4096 bitlines （BLs）. Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm tech- nology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines （WLs） and 4096 bitlines （BLs）. Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

关 键 词：NOR flash memory giga-level 65 nm technology array efficiency high speed 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TP333.35[自动化与计算机技术—计算机科学与技术]