多核混合可重构计算系统MRCS的设计  

Design of hybrid architecture of multi-core reconfigurable computing system MRCS

作　　者：倪伟[1] 邵响 张溯[1] 宋宇鲲[1] 杨延辉 卜冀春 

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009 [2]中科龙泽信息科技有限公司,无锡214072

出　　处：《电子测量与仪器学报》2015年第2期172-178,共7页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(61204024);国家自然科学基金(61179036);江苏省自然科学基金(BK2011185)资助项目

摘　　要：设计了一种面向计算密集型应用的多核混合架构可重构计算系统MRCS。其可重构处理器中的可重构阵列计算单元负责密集规则的运算,浮点处理器负责离散运算,配合灵活的本地缓冲,有效地提高了多核可重构计算系统对算法的适应性。实现了一个能够稳定地运行在100 MHz的基于FPGA的MRCS原型,并通过分别映射大维度浮点矩阵乘法、IDCT算法和运动估计算法进行性能验证。实验结果表明MRCS具有更高的计算效率和灵活性。Hybrid architecture of multi-core reconfigurable computing system,named MRCS,is designed for compute-intensive oriented application. In MRCS,reconfigurable array computing units perform the task of dense and regular operations; floating point units are responsible for the discrete computing operations. In addition,with flexible local buffers,this architecture could effectively improve the adaptability of reconfigurable computing system to application. An FPGA based MRCS prototype which could operate steadily at 100 MHz has been implemented.With mapping of the large-dimensional floating-point matrix multiplication,IDCT algorithm and motion estimation algorithm,the computing performances are validated. The experimental results show that MRCS has higher computing efficiency and flexibility.

关 键 词：可重构处理器 MRCS 多核可重构计算 密集型计算 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]