一种DSP指令Cache的功耗优化策略  

A Power Optimization Strategy of Directive Cache on DSP

作　　者：单悦尔[1,2] 杨兵[1,2] 于宗光[1,2] 曹华锋 

机构地区：[1]江南大学物联网学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子器件》2015年第1期214-217,共4页Chinese Journal of Electron Devices

基　　金：江苏省333工程科研项目(BRA2011115)

摘　　要：高性能DSP器件对功耗指标要求越来越高,功耗主要来源于对存储空间的访问,因此提出了一种改进型Cache功耗优化策略,实现了对指令Cache的分阶段访问,同时兼顾了Cache的动态功耗和静态漏流功耗的优化,改进了传统的基于非分阶段访问的按需唤醒策略NPOWP(Non-Phased Cache with On-Demand Wakeup Prediction)显著影响处理器性能的缺点。设计应用于DSP设计的4路组相连昏睡指令Cache中,使用基于分阶段访问的按需唤醒策略POWP(Phased Cache with On-Demand Wakeup Prediction)策略平均可降低75.4%的指令Cache功耗,降低6.7%的处理器总功耗,性能损失仅为0.77%.Power target has become much stricter for high-performance DSP design. An improved Cache power optimization strategy is put forward,directive Cache phased access is realized,and at the same time,the optimization of power cache and static leakage power is taken into account,which improves traditional optimization methods to raise processor performance. As a result,traditional NPOWP strategy has a significant affect on the processor performance. According to the results of different strategy simulations,it is applied to the design of a four-group connected instructions Cache,using the POWP strategy can reduce the average 75. 4% of the instruction Cache power and the total processor power consumption 6. 7% with the performance loss of only 0. 77%.

关 键 词：DSP Cache功耗优化 NPOWP策略 静态漏流功耗 功率优化策略 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN73