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机构地区:[1]Institute of Microelectronics, Chinese Academy of Sciences
出 处:《Journal of Semiconductors》2015年第2期144-150,共7页半导体学报(英文版)
基 金:Project supported by the National High Technology Research and Development Program of China(No.2011AA010403);the National Natural Science Foundation of China(No.61474134);the National Science and Technology Major Project(No.2014ZX02302002)
摘 要:A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.
关 键 词:clock and data recovery frequency and phase tracking digital filter bang bang PD phase interpolator
分 类 号:TN919.2[电子电信—通信与信息系统]
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