一种1394b PHY快速锁定时钟恢复电路的设计  

Design of a Fast Locking Clock and Data Recovery Circuit of 1394b PHY

作　　者：唐龙飞 田泽 王晋 

机构地区：[1]中国航空计算技术研究所,陕西西安710119

出　　处：《计算机技术与发展》2015年第3期146-149,共4页Computer Technology and Development

基　　金：总装备部预研基金项目(9140A08010712HK6101)

摘　　要：为了满足多通道1394b串行收发器芯片对时钟恢复电路锁定时间和相位精度的需求,文中提出了一种快速锁定时钟恢复电路,通过循环移位寄存器控制模拟插值器来实现。该时钟恢复电路通过环形振荡器产生多相时钟,并通过基于差分电荷泵的PLL电路降低了输出时钟信号的抖动;通过将输入数据相位与多相时钟信号进行比较,确定合成输出时钟信号需要的输入时钟相位;通过循环移位寄存器控制模拟插值器的电流,改变输出时钟相位,直至其与输入数据相位锁定。该电路可以解决延迟锁相环时钟恢复电路速度和精度不够的问题。该电路在0.13μm CMOS工艺下实现,可以工作于0.1-1 GHz。当工作电压为1.2 V,输入数据速率为1 Gbps时,电路的功耗为0.8 mW,最小相位变化为3.5 mUI。In order to meet the needs of locking time and phase accuracy of clock recovery circuit for 1394 b serial transceiver multi channel chip,propose a fast locking clock recovery circuit through analog phase interpolator controlled by shift register in this paper. The clock recovery circuit generates the multiphase clock through a ring oscillator,and reduce the output clock jitter of PLL by a differential charge pump. The input clock phase of CDR circuit is determined by comparing the input data phase with the multiphase clock phase. The shift register changes the current of analog interpolator and so the output clock phase of the CDR circuit,until the output clock phase is locked with the input data. The circuit can solve the problem of insufficient precision and speed encountered by delay PLL circuit. The circuit is realized under 0. 13 μm technology and can work at 0. 1 - 1 GHz. At 1. 2 V operating voltage and 1 Gbps data rate,the power is 0. 8 mW and the minimum phase shifter is 3. 5 mUI.

关 键 词：模拟插值器 差分电荷泵 时钟恢复 快速锁定 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]