并行处理二维图形加速引擎结构设计  

Architecture design for parallel processing 2D graphics accelerating engine

作　　者：田泽[1] 韩立敏[1] 张骏[1] 任向隆[1] 

机构地区：[1]中国航空工业西安航空计算技术研究所,陕西西安710068

出　　处：《计算机工程与设计》2015年第3期823-828,共6页Computer Engineering and Design

摘　　要：为提升二维图形操作的执行效率,提出一种并行计算结构的二维图形加速引擎,能够同时对典型的二维图形、文本和图像进行处理,显著增强二维图形图像的处理效率。基于Xilinx Virtex6xc6v1x760构建FPGA原型系统,进行功能验证和性能评估,评估结果表明,相比Marvell PXA300,该二维图形加速器能更加有效地加速二维图形操作,CPU使用硬件调用在加速引擎上执行二维图形操作比软件执行平均快23倍,在SMIC 65nm CMOS工艺下,加速器的工作速度可达325 MHz,满足设计需求。To improve executing efficiency of 2Dgraphics operations,aparallel processing accelerator for typical 2Dgraphics,image and text was proposed.Functional verification and performance evaluation were carried out on FPGA prototype system constructed using Xilinx Virtex6xc6v1x760.As a result,compared to Marvell PXA300,the accelerating engine has an obvious improvement on accelerating 2Dgraphics operations.Compared to software rendering,when 2Dgraphics operations are executed on the accelerating engine,it can be speeded up by 23 times on average.Its operating frequency can reach 325 MHz using SMIC65 nm CMOS technology,which meets design requirements.

关 键 词：图形处理器 二维图形 硬件加速器 光栅操作 位图 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]