惯导输出模拟器设计  

Design of Simulator about INS Output

作　　者：张志文[1] 吴浩[1] 

机构地区：[1]西安工业大学电子信息工程学院,西安710021

出　　处：《计算机测量与控制》2015年第3期972-974,978,共4页Computer Measurement &Control

摘　　要：针对惯导组件产品测试中多种信号的输出,设计一种基于FPGA惯导组件输出模拟系统;以FPGA芯片为核心,在Quartus II软件开发平台上使用Verilog语言进行编程然后生成原理图,设计DDS(direct digital synthesizer)信号发生器来输出48路脉冲信号,实现对4个惯导组件输出的48路脉冲信号模拟;在FPGA中采用Verilog硬件描述语言编写8串口发送代码生成原理图,实现对8个惯导组件输出8路串口数据的模拟;通过人机交互界面的按键和液晶对脉冲输出和串口发送的参数进行调节,实现脉冲输出和串口发送的设定;利用DDS技术设计48路脉冲较其他方法精度更高,利用FPGA的并行运算特点实现8路串口数据的并行发送;设计降低了各种测试信号连接时的复杂度,提高了测试信号的稳定度和惯导组件标定的效率。For a variety of tests of INS output signal component products , designed to simulate FPGA inertial system based on component output. The system FPGA chip as the core, using Verilog language in the Quartus II software development platform for programming and generate schematics, design DDS （Direct Digital Synthesizer） signal generator to output a 48--channel pulse signal, the output of the four components of INS the 48 channel pulse signal simulation. Using Verilog hardware description language code generation 8 serial send schematics, INS components to achieve the eight serial data output 8--channel analog in the FPGA. Through interactive interface buttons and LCD on the parameters of the pulse output and serial transmission is adjusted to achieve set the pulse output and serial transmission. This design reduces the complexity of the various test signals connected to improve the stability of the test signal components and the inertial eali bration efficiency.

关 键 词：惯导组件 脉冲 串口 精度 并行 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]