弹载小型化高速信号处理机设计方案  

Design Scheme of Missile-borne Miniaturization High-speed Signal Computer

作　　者：庄跃迁[1] 

机构地区：[1]中国西南电子技术研究所,成都610036

出　　处：《电讯技术》2015年第3期286-290,共5页Telecommunication Engineering

摘　　要：弹载处理机受特殊的平台功能、环境条件等因素制约,具有高性能、小型化等特点。弹载小型化高速信号处理机采用基于多通道宽带采样技术和多核心高速并行处理技术的设计方案,解决了高速高密度小型化电路设计和高速浮点数字信号处理器(DSP)多核心协同工作两大关键技术,并在不影响处理机实时性的前提下,设计出了一种基于嵌入式操作系统设计理念的多核心协同工作框架软件。弹载处理机可满足弹载多领域的功能和指标需求。Constrained by the special platform functions and environmental conditions, missile-borne com- puters have the characteristics of high-performance and miniaturization. Missile-borne miniaturization high -speed signal computer adopts the design scheme based on the technologies of multi-channel wide-band sampling and multi-core high-speed parallel processing. The scheme solves two key technologies, including the design of high-speed and high-density miniaturization circuit, and the multi -core collaborative working of high-speed floating-point digital signal processor（DSP）. The multi-core collaborative framework soft- ware based on the design concept of embedded operating system is designed. The missile-borne computer meets the requirements of function and index in multi-field of missile-borne.

关 键 词：弹载处理机 小型化设计 数字信号处理器 多核心协同 

分 类 号：TN876[电子电信—信息与通信工程]