基于关键路径延时检测的自适应电压缩减技术  

Adaptive Voltage Scaling Technique Based on Critical Path Delay Monitoring

作　　者：秋攀 乔树山[1] 凌康[1] 孙晓蕾[1] 赵慧冬[1] 宋强国[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2015年第4期250-254,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61306025;61474135)

摘　　要：为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗。自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压。本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4%,11.3%,10.4%和11.6%。In order to reduce the voltage margins produced by the conventional worst-case design method,a variation-aware adaptive voltage scaling（ AVS） technique was presented to save power consumption by tunning the supply voltage. The AVS technique is based on observing the timing variation in critical paths. For this task,a pre-error in-situ delay monitor was proposed which was capable of monitoring the critical path delay. The AVS control unit tunes the supply voltage according to the count of preerror which is produced by the monitor. The chip was designed in SMIC 180 nm technology. The simulation results show that the power consumption of 4 test circuits with AVS technique are reduced by12. 4%,11. 3%,10. 4% and 11. 6% respectively.

关 键 词：自适应电压缩减(AVS) 预错误 原位延时检测 关键路径 低功耗 

分 类 号：TN492[电子电信—微电子学与固体电子学]