L32嵌入式处理器动态流水线的设计与实现  

Design and Implementation of Dynamic Pipeline for L32 Embedded Processor

作　　者：张云龙[1] 来智勇[1] 刘志鹏[1] 

机构地区：[1]西北农林科技大学信息工程学院,陕西杨凌712100

出　　处：《微电子学与计算机》2014年第12期34-37,共4页Microelectronics & Computer

摘　　要：L32嵌入式处理器是自主研发的一种CISC 32位处理器,面向控制领域,能进行32位、16位、8位和1位算数逻辑运算,其三级流水线结构已通过Verilog HDL实现和验证.以此为基础,设计并实现了一种六级动态流水线方案,把原需要两个时钟周期的加法器拆分为两级,提高了8位数的运算速度;把原执行级按最慢指令执行周期分为4级,但每条指令无需都经过这4级,既实现了需要多时钟周期执行指令的并行执行,又能使原只需要一个时钟周期执行的指令一个时钟周期后就能执行完毕.通过NC-verilog综合验证和Debbusy波形分析,结果显示所设计的六级动态流水线方案有较高的吞吐率.A L32 embedded processor,mainly used in the control field,is one of our self-developed CICS 32-bit processors.It is able to perform arithmetic and logic operations of 32-bit,16-bit,8-bit and 1-bit,and the threestage pipeline structure of which has been realized and verified by Verilog HDL.Based on this,a six-stage dynamic pipeline program is designed and implemented in this paper.By splitting the original adder which requires two clock cycles,into two stages,the computational speed of eight decimals has been improved.In this scheme,the former execution stage is divided into four stages according to the slowest instruction execution cycles.Since not all execution need to go through these four stages,this scheme not only realizes the parallel execution of instructions that need multiple clock cycles,but also finishes in a clock cycle for instructions that need only one clock.Through comprehensive verification of NC-verilog and waveform analysis of Debbusy,it is shown that the proposed method of six-stage dynamic pipeline enjoys a high throughput.

关 键 词：嵌入式处理器 动态流水线 加法器 并行执行 吞吐率 

分 类 号：TN402[电子电信—微电子学与固体电子学]