基于SystemC的MIPS处理器建模与架构  

SystemC based MIPS processor modeling and architecture

作　　者：彭德生 蒋志翔[1] 

机构地区：[1]中国航天科工集团第二研究院706所,北京100854

出　　处：《计算机工程与设计》2015年第4期1015-1021,共7页Computer Engineering and Design

摘　　要：为研究系统建模应用于处理器架构设计、性能分析的方法,基于SystemC建模语言,提出一种"结构框图-模块细化-模型映射"自顶向下规范化的系统模型建立方法,以此方法建立MIPS(microprocessor without interlocked piped stages)架构处理器的周期精确模型。研究用系统级模型进行系统架构设计的方法,分析不同高速缓存Cache的设计对处理器性能的影响。仿真结果表明,L1(Level 1)级Cache采用2路或4路、容量在4KB到32KB之间比较合适。To study the system modeling method applied on processor architecture designing and performance analyzing with the standardization of SystemC modeling language,a top-down normalized system modeling method called system block diagrammodule refining-model mapping was proposed based on SystemC.On this basis,a cycle-accurate MIPS（microprocessor without interlocked piped stages）processor model was built.To explore the way of system architecture designing using the model proposed,the influence of a variety of Cache designs on system＇s performance was studied.The simulation results indicate it is appropriate to adopt 2-way or 4-way Cache with the capacity in the range of 4KB to 32 KB.

关 键 词：SYSTEMC 系统建模 系统仿真 架构设计 MIPS处理器 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]