An Implementation of ARM Debugger based on Ethernet Interface  

作　　者：XU Xuehui 

机构地区：[1]College of Electronic Information Engineering, Wuhan Polytechnic, Wuhan 430074, China

出　　处：《International Journal of Technology Management》2015年第2期72-74,共3页国际技术管理

摘　　要：To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; Logic Design

关 键 词：JTAGLink Debugger ETHERNET FPGA Logic Design 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术] TP311.52[自动化与计算机技术—计算机科学与技术]