基于FPGA的静止电压稳定优化器设计  

Design of Static Voltage Stabilizer&Optimizer Based on FPGA

作　　者：黄勇[1] 陈慈发[1] 韩帅[1] 李克成[2] 罗凯[2] 

机构地区：[1]三峡大学计算机与信息学院,湖北宜昌443002 [2]三峡大学电气与新能源学院,湖北宜昌443002

出　　处：《计算机测量与控制》2015年第4期1339-1342,共4页Computer Measurement &Control

摘　　要：基于FPGA设计的Buck-Boost型静止电压稳定优化器,直接串联于市电与敏感负荷之间,当供电电压发生电压骤升或骤降时,可快速稳定电压,确保敏感负荷不受影响;采用前端整流装置代替固定储能装置可获取更长的故障穿越时间,采用单同步旋转坐标系软件锁相环(SSRF-SPLL)技术实现电网电压同步,而采用电压双闭环控制技术改善了系统的响应速度;试验结果表明,该装置能快速稳定电压骤升骤降,并能较好地抑制谐波。The design of Buck Boost type static voltage stability optimizer based on FPGA, directly connected in series between the mains supply and the sensitive loads, when the supply voltage occurs sags or swells, it fastly stable the voltage to ensure that the sensitive loads are not affected. Using rectifier circuit in head instead of a fixed energy storage device to get a longer fault ride-- through time, the use of base on single synchronous rotating coordinate system software PLL technology to synchronize the voltage of mains, dual closed--loop control system is adopted to improve the speed of response. The experimental results show that the device can quickly stabilize voltage surges and sags, and then can suppress the harmonies effectively.

关 键 词：大规模可编程阵列 升降压 静止电压稳定优化器 电能质量 

分 类 号：TP303.3[自动化与计算机技术—计算机系统结构]