高端路由器8口万兆子卡的硬件设计  

Hardware design of high-end routers' eight-port 10Gb E daughter board

作　　者：齐剑[1,2] 胡春晖[1,2] 

机构地区：[1]光纤通信技术和网络国家重点实验室,湖北武汉430074 [2]武汉烽火网络有限责任公司,湖北武汉430074

出　　处：《电子设计工程》2015年第7期178-181,共4页Electronic Design Engineering

摘　　要：首先详细介绍了高端路由器的八口万兆子卡的功能和硬件架构。然后结合子卡的PCB设计和信号完整性,探讨了PCB叠层设计,利用Polar SI9000软件计算传输线阻抗和线宽以及布线时超高速差分线应注意的规则,最终设计方案通过了测试,投入了市场,验证设计方案的实用性。The paper first introduces the function and hardware architecture of high-end routers＇ eight-port 10GbE subcard. Secondly,according to PCB design of daughter board and signal integrity,the paper discusses design of PCB stack ,calculates impedance and line width of transmission line with Polar SI9000, and discusses rules of super speed different line when wiring. Finally,the design comes through the test,and launchs into market, verifying the practicability of the design.

关 键 词：八口万兆子卡 PCB叠层设计 阻抗 差分线 信号完整性 

分 类 号：TN919.5[电子电信—通信与信息系统]