百万门级系统芯片低功耗技术研究  

Study on Techniques of Reducing the Power for Million-Gate System Chip

作　　者：于宗光[1,2] 杨兵[1,2] 魏敬和[1,2] 单悦尔[1,2] 曹华锋 

机构地区：[1]江南大学物联网学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2015年第2期217-220,224,共5页Microelectronics

摘　　要：针对超大规模集成电路低功耗设计技术市场需求的迅速增大,提出了一种新的百万门级系统芯片低功耗设计流程,重点分析了芯片系统级、电路级、逻辑级与物理级四个不同的层次的低功耗设计方法,包括系统构架、时钟与功耗管理算法等低功耗关键技术。以某新型雷达SoC低功耗设计为例,采用SMIC 0.18μm 1P6M CMOS工艺进行设计,版图尺寸为7.825 mm×7.820mm,规模约为200万门。实验结果表明,在100MHz工作频率下,采用新的低功耗设计流程后,前端设计阶段功耗降低了42.79%,后端设计阶段功耗降低了12.77%,芯片总功耗仅为350 mW。样品电路通过了用户某新型相控阵雷达系统的应用验证,满足小型化和低功耗的要求。The demand of low power techniques of ULSI was increased rapidly.A kind of design flow to reduce the power for million-gate system chip was put forward.The low-power methods were emphasized from system level,circuit level,logic leve1 and physical leve1.The critical techniques were presented including the low power system architecture and the arithmetic of the clock-power management.A radar SoC was designed in SMIC 0.18μm1P6Msalicide CMOS process.The area was 7.825mm×7.820 mm,and the integration scale was about 2millions.The results showed that the power consumption was reduced by 42.79% during fore-end phase and was reduced by12.77% during back-end phase at the operating frequency of 100 MHz.The SoC chip met the 350 mW design specification,which had passed the test on the modern radar application system.It met the requirements of the miniaturization and low power systems.

关 键 词：低功耗 百万门级 系统级 电路级 逻辑级 物理级 

分 类 号：TN432[电子电信—微电子学与固体电子学]