嵌入式存储器容错方案可靠性评估  

Impact Analysis of Soft Error Mitigation for Embedded Memories

作　　者：支天[1,2] 杨海钢[1] 蔡刚[1] 秋小强[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100190

出　　处：《微电子学》2015年第2期275-280,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61204045;61271149);中国科学院;国家外国专家局创新团队国际合作伙伴计划资助课题(2013ZX03006004)

摘　　要：随着工艺节点的不断降低,存储器的软错误率呈指数趋势上升,容错技术已成为存储器设计中的重要环节。依据美国NASA Rosetta实验数据,对错误检纠错码(EDAC:Error Detection and Correction)和不同的在线刷新模式组成的多种容错方案进行可靠性建模与量化评估,提出了不同工艺节点下嵌入式存储器容错技术选择的判据方法。在地面单粒子模拟实验中进行验证,结果表明,该方法预测的失效率评估结果与实验测试结果的平均偏差约为10.3%。History had shown that memory technology shrinks as the system density grew,and at the same time,user expectation of system uptime increased.Given this,new mitigation technologies would be required to reduce the impact of memory faults.Error detection and correction code（EDAC）and two dynamic memory scrubbing schemes with various type of anticipated memory failures were shown.A way to select the appropriate mitigation technology for embedded memories in different technology nodes was proposed.Experimental investigations were performed using heavy ion accelerators.The result of 10.3%average error verified the effectiveness of the proposed model.

关 键 词：可靠性评估 容错技术 嵌入式存储器 

分 类 号：TN406[电子电信—微电子学与固体电子学]