基于FPGA的GPS同步时钟系统设计  

Design of GPS synchronized clock system based on FPGA

作　　者：郑恭明[1] 沈媛媛[1] 

机构地区：[1]长江大学电子信息学院,湖北荆州434023

出　　处：《桂林理工大学学报》2015年第1期198-201,共4页Journal of Guilin University of Technology

基　　金：中国石油科技创新基金项目(2011D-5006-0302);湖北省教育厅科学研究项目(B2013279)

摘　　要：结合恒温晶振时钟无随机误差和GPS秒信号无累计误差的特点,采用GPS测量监控技术,对高精度晶体振荡器的输出频率进行精密测量和校正后作为系统时钟,通过相位同步算法使FPGA的输出PPS信号与GPS的PPS信号同步。系统中使用Nios II+Verilog HDL设计了高分辨率的时间测量和快速校准时钟同步单元,缩短了频率校准和同步时间。实验结果表明:系统同步精度较高、结构简单,并成功地应用于电磁勘探数据采集系统中。GPS-clock,free of cumulative error and the high precision crystal oscillator,free of random error,thus can be effectively combined.By advanced GPS monitoring and controlling technology,the output frequency of the crystal oscillator is measured and adjusted,by synchronizing FPGA_PPS with GPS_PPS by phase synchronization algorithm. A high-resolution fast-measuring unit and clock synchronized unit are designed by Nios II＋Verilog HDL to reduce the time of calibration and synchronization.After experimental verification,the high precise telegraphic synchronized system can be successfully applied in data acquisition system of electromagnetic survey.

关 键 词：GPS 时钟同步 恒温晶振 FPGA 

分 类 号：TM764[电气工程—电力系统及自动化]