面向高精度互连时延分析的电路网表生成方法  

A Generation Method for the High-precision Interconnect Delay Analysis of Circuit Netlist

作　　者：赵陈粟[1,2] 齐明[2] 喻文健[2] 

机构地区：[1]山东英才学院信息工程学院,济南250104 [2]清华大学计算机科学与技术系,北京100084

出　　处：《科学技术与工程》2015年第9期97-102,共6页Science Technology and Engineering

基　　金：北京市自然科学基金(61076034)资助

摘　　要：面向高精度时延分析,提出基于场求解器电容提取的自动互连电路网表生成方法。通过分析三维互连结构数据,实现互连线网中导体块之间连接关系判断;然后用图的广度优先遍历算法重新排序导体块,最后结合电阻电容提取结构生成SPEF和SPICE两种电路网表。基于实际互连结构的实验验证了该方法的正确性和有效性。For high-precision delay analysis,a netlist generation method of automatically interconnect circuit based on field solver capacitance extraction is proposed.Firstly,the connection relationship between conductors in the interconnection network can be checked according to analyses of the three-dimensional interconnect structure data.Then the figure breadth-first calendar calculation method to reorder again conductor block is used.Finally,resistance and capacitance extraction structure is combined to generate SPEF and SPICE two kinds of the circuit netlist.The actual interconnection structure of the experiment shows the correctness and validity of the method.

关 键 词：三维互连结构 时延分析 电路网表 SPEF SPICE 

分 类 号：TN47[电子电信—微电子学与固体电子学]