一种TIADC系统时钟偏斜误差的全并行校正方法  

A full parallel correction method of time skew error for TIADC system

作　　者：聂伟[1] 邱蓉[1] 

机构地区：[1]北京化工大学计算机系统与通信实验中心,北京100029

出　　处：《实验技术与管理》2015年第4期47-51,共5页Experimental Technology and Management

摘　　要：给出了一种TIADC系统时钟偏斜误差全并行结构的校正方法。该方法利用串并转换实现高速数据的降速,再利用滤波器的多相分解技术构建一个16×16的滤波器阵列对时钟偏斜误差进行实时校正,不但可以有效地减小杂散频谱,而且当输入信号从10 MHz变化至500 MHz时,系统校正后的SFDR平均提高了30.64dB。仿真结果表明了该方法的正确性和有效性。This paper presents a full parallel correction method of time skew error for TIADC system.And the method can not only utilize serial-to-parallel conversion to realize reduction of speed for high speed data,but also make use of polyphase decomposition technique to build a 16×16filter array to correct the time skew error in real time.The time skew error can be largely and well calibrated by this method,moreover,When the input signal changes from 10 MHz to 500 MHz,the SFDR of the system after correction raises 30.64 dB averagely.The simulation results indicate the correctness and effectiveness of the method.

关 键 词：TIADC系统 时钟偏斜误差 完美重构 全并行校正 

分 类 号：TN713[电子电信—电路与系统]