PLL驱动DDS的低相噪小步进LFM信号源设计  

Design of a LFM Signal Source with Low Phase Niose and Small Frequency Step Based on PLL Driver DDS

作　　者：王文才[1] 陈昌明[1] 黄刚[1] 

机构地区：[1]成都信息工程学院通信工程学院,成都610225

出　　处：《电子器件》2015年第2期348-351,共4页Chinese Journal of Electron Devices

基　　金：四川省教育厅自然科学重点项目(13ZA0087)

摘　　要：介绍了一种低相噪线性调频(LFM)雷达信号源的产生和实现方案。通过分析DDS输出信号频谱和杂散,采用HMC704控制VCO的方法设计了1 GHz的锁相环路(PLL)作为DDS的时钟驱动电路,并对环路滤波器和AD9910硬件电路优化设计改善杂散和相噪性能。通过计算寄存器参数和分析SPI总线时序,利用FPGA对DDS和PLL高速配置。最后给出了系统实物图和测试方法,实测结果表明:该线性调频源输出幅度大于-3dBm,频率步进为1kHz,相位噪声优于-103dBc/Hz@1kHz,各项指标满足实际工程要求。The method of generating and implementing a kind of linear frequency modulation（ LFM） radar signals with low phase noise is introduced. The 1 GHz PLL is designed as DDS＇s clock driver circuit using HMC704 control VCO by analyzing the spectrum of the output signal and the DDS spurious. The loop filter and AD9910 hardware circuit is also optimized in order to improve the phase noise and spurious. The register parameters is calculated and SPI bus timing is analyzed,DDS and PLL is configured high-speedy by FPGA. Experimental results show that the LFM source output amplitude greater than- 3dBm,frequency step is 1kHz,the phase noise is better than- 103 dBc/Hz@ 1kHz,the indicators meet the practical engineering requirements.

关 键 词：频率源 线性调频 PLL+DDS(锁相环-直接数字系统) AD9910 HMC704 

分 类 号：TN74[电子电信—电路与系统]