一种900V超结VDMOSFET器件的设计与仿真  

Design and Simulate of High Voltage S-J VDMOSFET

作　　者：杨永念 

机构地区：[1]重庆邮电大学光电工程学院,重庆400065

出　　处：《电子与封装》2015年第3期29-34,共6页Electronics & Packaging

基　　金：重庆市教委科学技术研究项目(KJ120505)

摘　　要：功率MOSFET在现代电子工业中已经得到了广泛的运用,然而在高压功率MOSFET器件中,如何平衡功率MOSFET的击穿电压与导通电阻的冲突一直是研究热点。结合超结理论和传统功率VDMOSFET的生产工艺设计了一款高压超结VDMOSFET器件,运用半导体器件仿真软件对器件结构进行优化,得到P柱区和N柱区掺杂浓度和厚度的最优值和工艺参数。仿真结果表明,设计的超结VDMOSFET器件击穿电压和导通电阻分别为946 V和0.83Ω,很好地平衡了功率MOSFET击穿电压与导通电阻的冲突。Power MOSFET in modem times has been widely used in electronic industry. In high-voltage power MOSFET device, it＇s still not solved that how to balance the contradiction of the breakdown voltage and the on resistance of power MOSFET. The article combine with super-junction theory and manufacturing process of the traditional power VDMOSFET to design a high voltage super-junction MOSFET, and using the semiconductor device simulation software to optimize the structure of device. Get column P and N column of doping concentration and thickness of the optimal value and process parameters. The simulation results show that the S-J VDMOSFET with breakdown voltage of 946 V and on resistance of 0.83 Ω It solved the conflict of balance between the breakdown voltage and on resistance of the power MOSFET perfectly.

关 键 词：功率MOSFET 超结VDMOSFET 导通电阻 击穿电压 

分 类 号：TN305[电子电信—物理电子学]