基于FPGA的数据采集测试系统设计  

Data Acquisition Test System Based on FPGA

作　　者：黄远望 严济鸿[2] 周伟[3] 

机构地区：[1]西南通信研究所,成都610041 [2]电子科技大学电子工程学院,成都611731 [3]南京电子技术研究所,南京210039

出　　处：《现代雷达》2015年第4期73-76,80,共5页Modern Radar

摘　　要：为满足某数模转换器(Analog-Digital Converter,ADC)测试平台的需求,设计并实现了一种基于通用串行总线(Universal Serial Bus,USB)接口的双通道数据采集测试系统。该系统以现场可编程门阵列(Field Programmable Gate Array,FPGA)为核心,采用高速静态随机存储器(Static Random Access Memory,SRAM)作为数据缓存,支持多种触发模式和数据采集模式,同时兼容多种数据缓存长度的设置。系统采用CYPRESS公司USB芯片的Slave FIFO模式实现数据的传输和指令的交互。上位机应用程序以指令方式对下层硬件的数据采集过程进行控制,同时可显示波形和对ADC各项动态静态参数的计算分析。整个系统由板级硬件、FPGA内部逻辑、USB固件程序、设备驱动和上位机软件构成。经过测试,系统可实现采样率为4 MHz时ADC输出信号的稳定采集,并得到较好的ADC参数测量结果,验证了设计方案的正确性和可行性。This paper designs a USB-based dual channel data acquisition system and realizes it to meet the requirements of an cer- tain experiment platform of ADC. This system uses FPGA as control core, with high-speed SRAM performing as data caching. Multiple trigger modes and data sampling modes are supported in the system, as well as settings for the data caching length of many kinds . It transfers data and command between computer with the hardware by Slave FIFO interface of USB chip of CYPRESS cor- poration. The application program in PC controls the data acquisition process by means of instruction, also completes waveform display while analysizing and computing the received data for the ADC parameters . The entire system is composed of hardware, logic circuit inside the FPGA, USB firmware, USB device driver and application program. In the test, this system acquires the signal whose sample rate is 4MHz effectively with good ADC testing results. The test result testifies that this project is correct and valid.

关 键 词：现场可编程门阵列 通用串行总线 数据采集 双通道 ADC性能测试 

分 类 号：TN791[电子电信—电路与系统] TP274.2[自动化与计算机技术—检测技术与自动化装置]