基于FPGA的自适应TIADC数据采集  

Design of Adaptive TIADC Data Acquisition Based on FPGA

作　　者：叶忠辉 蒋志迪[1] 汪鹏君[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《数学的实践与认识》2015年第8期235-241,共7页Mathematics in Practice and Theory

基　　金：国家高技术研究发展计划(863计划)(2012AA091802);国家级星火计划项目(2014GA701019);浙江省科技计划项目(2013C31019)

摘　　要：通过对并行时间交替采样(Time-interleaved ADC,TIADC)理论和采样时间失配误差的研究,提出一种带时间补偿的自适应TIADC数据采集方案.方案首先产生具有等相位差的采样时钟,通过自适应电路估计时间失配误差;然后利用Farrow结构的分数延时滤波器对多通道采集数据进行校正,并交叉合并,得到高速TIADC数据;最后通过FPGA实验验证,证明自适应TIADC数据采集不仅可以提高采样率,而且能有效校正时间失配误差,保证数据采集的准确性.A design of adaptive TIADC data acquisition with time compensation is pro- posed by the study of parallel time-interleaved ADC （TIADC） theory and sampling time mismatch error. Firstly, sampling clocks with equal phase difference are generated from clock management, estimated time mismatch deviation by the adaptive circuit; then, the multi-channel data acquisition is corrected by Farrow structure＇ s fractional delay filter, and cross merged to obtain High-speed TIADC acquisition data;Finaly, the results of FPGA experimental verification show that adaptive TIADC acquisition system can not only increase the sampling rate, but also correct the time mismatch error effectively, thus ensure the accuracy of TIADC data collection.

关 键 词：自适应时间交替采样 Farrow滤波器 数据采集 FPGA 

分 类 号：TN713[电子电信—电路与系统] O174.2[理学—数学]