容工艺偏差的低偏斜层次化时钟网络设计  

Design of a hierarchical clock distribution network with low clock skew and tolerance for process variations

作　　者：王晓 柯希明 

机构地区：[1]国家高性能集成电路设计中心,上海201204

出　　处：《中国科学：信息科学》2015年第4期548-559,共12页Scientia Sinica(Informationis)

基　　金：国家科技重大专项"核高基"(批准号:2013ZX01028-001-001)资助

摘　　要：针对超深亚微米工艺出现的新特点,基于对称"H树"型全局时钟网络加区域化的"Mesh"时钟网格的混合时钟结构,实现了不同于传统全局Mesh结构的树形驱动本地网格层次化时钟分布网络.实验表明,该网络具有极低的偏斜和高工艺偏差容忍度,其总的时钟偏斜可控制在10 ps以内,其时钟偏斜随工艺变化值与设计值的偏差在10%的数量级上,极有利于高性能微处理器处理核心的时序设计.In this paper, a novel hierarchical clock distribution network is implemented with regard to the new characteristics of very deep sub-micro process. The clock distribution network is constructed with a mixed clock structure based on a global H-tree network and regional Mesh network. The regional Mesh network, which is also known as a local Mesh grid, is different from conventional global Mesh networks. Experiments indicate that this clock distribution network has a tiny clock skew and a high tolerance for process variations. The clock skew is within 10 ps. The impact of process variations on clock skew is in the ratio of 10%. These features are useful for timing sequence optimization of high-performance micro process cores.

关 键 词：H树 MESH 时钟分布网络 时钟偏斜 工艺偏差容忍度 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]