众核体系结构模拟研究进展  

Survey of ManyCore Architecture Simulation

作　　者：谢向辉[1] 郝子宇[1] 李宏亮[1] 陆晓亮[1] 张昆[1] 张健[1] 

机构地区：[1]江南计算技术研究所,无锡214000

出　　处：《高性能计算技术》2013年第1期11-18,共8页

摘　　要：众核处理器巨大的设计空间和复杂的设计方案为体系结构模拟提出了新的挑战，包括模拟结构复杂、模拟计算量大、宿主环境复杂等。为了应对这些挑战，需要开发出新的模拟技术、工具和模拟器，以降低模拟复杂度和实现难度、提高运行速度、增强模拟可配置性、提升模拟器易用一IAI通用性。本文展示了当前众核处理器体系结构模拟研究进展，包括各种模拟技术、模拟工具和模拟器实现，为众核体系结构模拟器理解、研究和实现提供参考。Because of its huge design space and complicated structure, the manycore issued many challenges for the architecture simulation, including speed, flexibility, expense, and ease of use. To address those bottlenecks, we need new simulation technique tools and simulators, which would reduce the simulation complexity accelerate the simulating speed and configure flexibly the simulating process. Based on this view, this paper surveys these recent developments about manycore architecture simulation, discuss the strengths and weaknesses of different approaches, and expect to help the future manycore simulation study.

关 键 词：体系结构模拟 众核 模拟技术 模拟工具 模拟器 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]