SOC系统中高效的卷积解交织实现结构  

Efficient Convolutional Deinterleaver in SOC

作　　者：黄戈[1] 何大治[2] 王白羽[1] 梁伟强[1] 管云峰[2] 

机构地区：[1]数字电视国家工程研究中心,上海200125 [2]上海交通大学,上海200240

出　　处：《电视技术》2015年第9期104-107,共4页Video Engineering

基　　金：国家自然科学基金项目(61221001;61102051;61420106008);111引智计划项目(B07022);国家高技术研究发展计划项目(2012AA011701;2013AA013503);上海交通大学科技创新基金项目(AF0300021)

摘　　要：目前ASIC芯片高度集成,针对解调芯片在SOC系统中的集成,设计了一种高效的卷积解交织实现结构,对地址产生及整形单元做了详细阐述,并以DTMB解调模块为例,描述实现过程及实现成果,该设计通过FPGA及ASIC的充分验证,结果证明,此方案设计具有高度的可靠性和稳定性,在SOC系统中极大提高了卷积解交织对总线的访问效率,极大降低了DDR的占用带宽。As the high ASIC integration demand increases, especially now demodulation module is integrated in SOC system, an ef- ficient convolution deinterleaver is designed, detailed address generation and shaping unit are described in detail, and using DTMB system as an example, the description of the implementation process and achieve resuhs through the full verification of both FPGA and ASIC are given. The results show that this design has a high degree of reliability and stability of the system in a SOC solution, and greatly improves the AXI bus access efficiency and extreme greatly reduced the DDR occupied bandwidth.

关 键 词：SOC 卷积解交织 ASIC 

分 类 号：TN949.197[电子电信—信号与信息处理]