采用输入输出分解的分区分段演化机制  

In-partition in-stage evolutionary mechanism by applying input and output decomposition

作　　者：姚睿[1] 陈芹芹[1] 孙艳梅[1] 张砦[1] 王友仁[1] 

机构地区：[1]南京航空航天大学自动化学院,江苏南京210000

出　　处：《哈尔滨工程大学学报》2015年第4期522-527,共6页Journal of Harbin Engineering University

基　　金：国家自然科学基金资助项目(61402226;61202001);中央高校基本科研业务费专项资金资助项目(XAA14036)

摘　　要：针对演化硬件的可扩展性问题,提出了基于输入输出分解的分区分段并行在线演化机制,用于演化组合逻辑电路。依据输入输出分解策略,将原电路分解为多个具有较少输入、输出的子电路,并对各子电路单独分配进化区域,实现各子电路的并行演化;某些子电路演化完毕,其对应进化区域即可用于其他任何未演化完毕子电路的并行演化;所有子电路均演化成功后,将其进行整合得到顶层电路。在Xilinx Virtex-5 FX构建的自演化系统上,以加法器电路、乘法器电路和部分MCNC基准电路为例进行了验证。结果表明:相对于经典演化方法,该方法可以大大减少演化时间,进化出多达21个输入的组合电路。To solve the problem of scalability of evolvable hardware, an in-partition in-stage parallel online evolution mechanism based on input and output decomposition is presented for evolving combinational logic circuit.According to the input and output decomposition strategy, the original combinational logic circuit is divided into several sub-circuits with fewer inputs and outputs.Each sub-circuit is assigned to a separate evolution area.This is constructed to realize the parallel evolution of sub-circuits.When the evolutions of some sub-circuits are completed, the corre-sponding areas of evolution can be used for the parallel evolution of any other sub-circuits with uncompleted evolu-tion.After the evolution on all sub-circuits are successfully completed they are integrated into a top circuit.In the self-evolving system built by Xilinx Virtex-5 FX, the adder circuit, multiplier circuit and partial MCNC benchmark circuits are taken as the examples for demonstration.The experimental results showed that compared to the classical evolutionary method, this method may greatly reduce the evolution time and evolve a combinational logic circuit with 21 inputs at most.

关 键 词：演化硬件 组合电路 输入输出分解 并行演化 演化算法 

分 类 号：TN929.5[电子电信—通信与信息系统]