一种多协议统一架构CMOS Serdes发送器电路设计  

Design of a Multi Protocol Unified Architecture CMOS Serdes Transmitter Circuit

作　　者：唐龙飞 田泽 邵刚 

机构地区：[1]中国航空计算技术研究所,陕西西安710119

出　　处：《计算机技术与发展》2015年第5期131-134,共4页Computer Technology and Development

基　　金："十二五"微电子预研(51308010601;51308010711);总装预研基金(9140A08010712HK6101)

摘　　要：为了满足SoC系统对多种高速串行通信协议的兼容性要求,文中提出了一种最高支持3.125 Gbps的多协议统一架构Serdes发送器电路结构,并在0.13μm CMOS工艺下实现。该结构通过分频比可编程的PLL电路来产生不同频率的时钟信号,并通过差分电荷泵电路降低了的分频比可调地降低了PLL电路输出时钟信号的抖动;通过上升/下降时间控制电路来改变输出信号的上升/下降沿时间,并通过控制信号来改变驱动器的输出信号幅度以及预加重幅度,从而满足不同协议对输出信号的上升/下降时间以及输出幅度的要求。测试结果表明,该发送器电路输出信号眼图可以满足PCI-E、Fiber Channel、SRIO等协议的模板要求,在3.125 Gbps速率下,其随机抖动RJRMS为1.81 ps。In order to meet the compatibility requirements of SoC system for a variety of high speed serial communication protocol,pro-pose a multi protocol unified Serdes transmitter architecture which can support maximum 3. 125 Gbps and has been realized in a 0. 13 μm CMOS technology. The dividing ratio of PLL can be programmed to produce different frequency,and the jitter of the PLL output clock is reduced through differential charge pump circuit. This transmitter architecture uses rising/falling edge control circuit to change the rise/fall time of the output signal,and uses control signal to change the amplitude and pre-emphasis amplitude of the driver so as to meet the different protocols requirements. Measurement results show that the output of the transmitter can meet the eye diagram template of the PCI-E,Fiber Channel and SRIO,the random jitter of the transmitter is 1. 81 ps at the rate of 3. 125 Gbps.

关 键 词：SERDES 发送器 低抖动 PLL 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]