宽带单载波频域均衡系统设计与FPGA实现  

Broadband Single Carrier-Frequency Domain Equalization system design and FPGA implementation

作　　者：杨刚[1] 李莹[1] 张小飞[1] 徐大专[1] 

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京210016

出　　处：《太赫兹科学与电子信息学报》2015年第2期226-232,共7页Journal of Terahertz Science and Electronic Information Technology

基　　金：国家自然科学基金资助项目(61371169);江苏省博士后科研资助计划项目(1201039C);中国博士后基金资助项目(2012M521099);江苏高校优势学科建设工程资助项目

摘　　要：单载波频域均衡(SC-FDE)是数字通信中克服多径衰落的有效技术。宽带通信系统中应用单载波频域均衡系统设计,实现137.5 MHz载波下27.5 Mbps的码元传输速率。同时在系统中添加1/2码率卷积码与(239,223)里德-所罗门(RS)码的级联信道纠错编码,提高系统的可靠性。完成单载波频域均衡系统设计,分析设计系统的关键技术,最终在现场可编程门阵列硬件平台上进行系统实现、调试和验证,完成系统实际误码率的测试。Single Carrier-Frequency Domain Equalization(SC-FDE) is effective to overcome multipath fading in digital communication and it is widely used for its performance. SC-FDE is adopted in broadband communication systems and a symbol transmission rate of 27.5 Mbps is realized under the carrier frequency of 137.5 MHz. The concatenated channel error correction coding of 1/2 rate convolution code combined with (239,223) Reed-Solomon(RS) code is used in order to improve the reliability of the system. The SC-FDE system is designed, and the key technologies of this system are analyzed. It is implemented on Field Programmable Gate Array(FPGA) hardware platform. The commissioning and validation are performed as well. The actual Bit Error Ratio(BER) test of the system is executed.

关 键 词：宽带单载波频域均衡 卷积码 里德-所罗门码 现场可编程门阵列设计 

分 类 号：TN914.3[电子电信—通信与信息系统]