基于IDCT模块的数据解码器的MMA结构设计  

MMA STRUCTURE DESIGN FOR IDCT MODULE-BASED DATA DECODER

作　　者：齐大彬[1] 李秋菊[2] 

机构地区：[1]辽宁科技大学,辽宁鞍山114044 [2]鞍山师范学院,辽宁鞍山114002

出　　处：《计算机应用与软件》2015年第5期182-184,共3页Computer Applications and Software

摘　　要：视频信息分解在解码过程中是一项很复杂的系统工程,IDCT是数据量集中运算方法中比较理想的选择。IDCT计算量小,满足MPEG-4标准,通过XVID解码器对相关文档解码过程中,IDCT需要运算的数据量大概为解码数据总量的四分之一。MPEG-4是音、视频解码标准,同步解码是这个标准的最重要特点,加快解码进程的关键方法是构建多媒体加速单元(MMA),取消以往使用纯软件实现过程。依据移动多媒体终端(SOC)的基础,构造了二维IDCT硬件加速器,在快速LLM算法基础上,完成了8点IDCT过程计算。在行列分解过程中,采用流水线技术,通过单转置存储器(RAM)处理,加快了数据处理进程,减少了芯片面积。通过MIPS+FPGA平台,进行软、硬件相关性协同分析,证明了设计过程的可行性,以及可以在便携式多媒体专用处理器中广泛应用。Video information decomposition is a very complicated system project in decoding process, IDCT （inverse discrete cosine transformation） is an ideal choice in centralised data volume operation methods. IDCT has small computational complexity and meets MPEG- 4 standard, in the process of decoding correlated documents using XVID decoder, the data volume to be operated by IDCT is approximately one fourth of total data amount decoded. MPEG-4 is audio and video decoding standard, and synchronised decoding is the most important feature of this standard, the key approach for speeding up the decoding process is to construct multimedia acceleration unit （MMA） , and to annul pure software realisation process used in the past. In this paper, we construct a 2D IDCT hardware accelerator based on mobile multimedia terminals＇ SOC, and complete 8 point IDCT process operation based on fast LLM algorithm. In rank factorisation process we adopt pipeline technology, through single transpose memory （RAM） processing, the data treatment process is accelerated, which decreases chip size. Coordinated correlation analyses for software and hardware are done through MIPS/FPGA platform, it verifies the feasibility of the design process, the design can be widely applied in portable muhimedia specialised processers.

关 键 词：反余弦变换 转置存储器 多媒体加速单元 多媒体终端 验证 

分 类 号：TP335.4[自动化与计算机技术—计算机系统结构]